have a project in which I have to implement an en/de-cryption structure using a standard AES block of 128-bits in VHDL and I think I'm a bit confused. So I'd like to ask some questions about AES and its modes of operation.
- When we say that we use a 128-bit key, does it mean that the data input's size is 128-bit or not? Generally can the block size be smaller than key?
- A block receives a plaintext. When the same block can receive a new plaintext?
- How can I perform each mode to make a system which encrypts information (parallel sequential)? I think that in NIST publication is clearly which modes can be performed pipelined or not. Although, I've been asked to find new ways of performance. What can I do? Please some help.