# AES block cipher modes of operation

have a project in which I have to implement an en/de-cryption structure using a standard AES block of 128-bits in VHDL and I think I'm a bit confused. So I'd like to ask some questions about AES and its modes of operation.

1. When we say that we use a 128-bit key, does it mean that the data input's size is 128-bit or not? Generally can the block size be smaller than key?
2. A block receives a plaintext. When the same block can receive a new plaintext?
3. How can I perform each mode to make a system which encrypts information (parallel sequential)? I think that in NIST publication is clearly which modes can be performed pipelined or not. Although, I've been asked to find new ways of performance. What can I do? Please some help.
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1. Input's size is only 128-bit for AES. When we use 192-bits or 256-bits key for AES the input's block size is 128-bit and not depend on the length of key.
2. The real question is not clear. Refine.
3. Go to the previous answers I want to add that there is CBC mode of AES. In CBC mode, each block of plaintext is XORed with the previous ciphertext block before being encrypted. This way, each ciphertext block depends on all plaintext blocks processed up to that point That is why we can't use parallel computing. To make each message unique, an initialization vector must be used in the first block.
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thank you for your answer. i tried to refine the 2 point of my question in a new question. I think i make a point of what i mean. –  George Karajohn Oct 8 '13 at 9:41