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Is there any freely available verilog implementaion of Diffie-Hellman key exchange?

I couldn't find anything using google. So, assuming its not there I started implementing on my own. The code is hosted at https://github.com/nulpoet/verilog_diffiehellman. Behavioral simulation in xilinx works. However it cannot synthesize the remainder(%) operator.

So, I does anybody know how to design a module for remainder operation in verilog that computes the remainder in a single clock cycle? Any links to literature discussing the algorithm would suffice.

Solution to any of the above two question would solve my problem.
Thanks in advance!

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1 Answer 1

Look on opencores within the vhdl section.

There are some older dos-era vhdl programs on simtel that have parsed-out statements so it might be more trouble than it is worth, but at least you could look under the hood of each function, grab what you need, run a lint checker etc, then perform verification.

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