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In many cryptographic protocols, some information is transmitted within smart cards. So, what is a smart card? Is it a physical card? What are they used for in cryptographic protocols?

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up vote 13 down vote accepted

A Smart Card is small portable physical device, typically flat and in the format of a traditional credit card (sometime much smaller: an example is the SIM card in a mobile phone), embedding:

  1. An Integrated Circuit with memory providing permanent data retention; that's using EEPROM, Flash, or FRAM in most of today's Smart Cards.
  2. Temporary coupling means with a reader device allowing to power that IC, and communicate with it; that may for example be contacts, often according to the ISO/IEC 7816-3 standard; or a few turns of conductive material in the card, forming an inductive loop operated at 13.56 MHz, often according to the ISO/IEC 14443 standard.
  3. Inhibiting means restricting read or/and write access to that memory according to some policy. This can go from a few logic gates, to microprocessor(s) with cryptographic accelerators for 3DES, AES, RSA, and ECDSA.

Wired logic Smart Cards

The first commercially successful Smart Card was a pre-paid phone card, used for over two decades in public phone booths in France, replacing coins (which made phone booths too much an attractive target). It had 256 bits of memory, implemented in EPROM technology with 21V programing voltage, plus one physical fuse. The contacts allowed to reset an 8-bit address counter, increment it, read the selected bit, and program the selected bit. Its memory access policy was: any bit can be read; any bit can be programmed (from 0 to 1) when the fuse is not blown; only the last 160 bits can be programmed when the fuse is blown (this is implemented by a logic function of the fuse's state and the three hight bits of the address counter); erasing (from 1 to 0, by exposing the bare IC to ultraviolet light) erases all bits, and normally occurs only in a late manufacturing stage of the IC. The first 96 bits contained issuing information, written before the fuse was blown. Some of the last 160 bits (as defined by issuing information) each represented a certain prepaid value, when still erased. Programming one of these bits reduced the remaining value in the Smart Card. Erasing did not help an adversary, for the issuing information could not be restored after erasure. That information was also protected by a checksum (a 7-bit field containing the binary expression of the number of 0 bits in like 88 other bits of that information; this corruption detection system is such that altering any number of bits in the same direction makes the information invalid).

Fraud by simulation (which was possible due to the lack of cryptographic protocol and secret key in that early Smart Card, and did occur) never was a seriously damaging issue, although about two billions of that Smart Card have been made. That was the kind preferred by Roland Moreno, often credited for the invention of the Smart Card circa 1974 (full disclosure: we have been close friends from 1983 till his death in 2012). Télécarte

Microprocessor Smart Cards

Many contemporary Smart Cards have a built-in microprocessor, usually on the same die as the long-term memory, implementing the access control policy, in the form of a program rather than wired logic. The access control policy can thus be almost arbitrarily complex (including contained in the memory itself, and alterable as part of the access control policy). That processor can be anything from a 1 MIPS 8-bit CPU, to a much faster 32-bit RISC core. There can be dedicated co-processors for cryptographic algorithms: DES/3DES, AES, RSA (and other cryptography based on exponentiation in $\mathbb{Z}_{n}$), ECDSA (and other cryptography based on elliptic curves), complete with sophisticated protection against side-channel attacks; hardware TRNG+PRNG with testability features; shield against intrusion; detectors of abnormal operating conditions (shield breach, light, temperature, supply voltage glitches..); bus encryption; parity or SECDED on memory; perhaps two CPUs, with hardware checking they obtain equivalent results, for added protection against fault injection attacks; and more.

For a tour (absolutely recommended) of a high-end Smart Card IC, see e.g. that Security Target (alternate link), starting with the block diagram on page 20.

Access control policy implemented in Smart Cards

As an illustration of a common feature, the Smart Card's permanent data memory can contain a Personal Identification Number and a counter of consecutive PIN presentation errors. The usual PIN access control policy will block PIN presentation if the counter of consecutive PIN errors reaches 3; increment the counter at each PIN presentation, then if the PIN is correct reset the counter and enable some function until power off: reading from or writing to some section of the memory; or/and using some information in the memory as the secret key of a cryptographic MAC allowing the Smart Card to be part of a challenge/response protocol. Such PIN policy makes the Smart Card safe against misuse in case of loss of the Smart Card without the PIN, with high confidence (0.03% risk for a 4-digit PIN).

Smart Cards are also useful a containers for an individual's or server's credentials in a Public-Key Infrastructure, in the form of a private key, generated within the Smart Card, or injected into it. The policy will typically include no function allowing the private key to leave the Smart Card, restricting the use of that key to, say, RSA signature of (the hash of) a message supplied to the Smart Card. That prevents compromise of the confidentiality of the key (but not misuse), should the Smart Card be connected to a compromised device/PC.

A lot of work goes into the access control policy of a modern Smart Card; see for example this (highly technical) two parts specification aimed at e-government applications; or (that's relatively simple) what pertains to the card in the European Regulation specifying the Digital Tachograph for trucks, in Annex 1B, appendix 2, and appendix 11 for the RSA + 3DES cryptography.

Comments on what ought to be added welcome!

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You have provided admirably plenty valuable informations. In a particular product:… there are stated: "The TOE provides full on-chip encryption covering the complete core, busses, memories and cryptographic co-processors leaving no plaintext on the chip." "No data in plain are handled anywhere on the TOE and thus also the two CPUs compute entirely masked and in addition dynamic mask changes are applied." Wouldn't that mean that homomorphic computations are being done there? – Mok-Kong Shen Jan 28 '13 at 10:39
@Mok-KongShen: The features described in your quotes (also in the very similar Security Target that I link to) are countermeasures against side channel leakage. Yes, computing on encrypted plaintext matches one characteristic of homomorphic computation. However, here, the device performing the computation can reconstruct the plaintext from what it manipulates, which goes against the goal of what's usually considered to be homomorphic computation. – fgrieu Jan 28 '13 at 20:41

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