Here is Ariel Gabizon's Blog for the process of converting Arithmetic Circuits into R1CS - https://electriccoin.co/blog/snark-explain5/
Here, he writes
We assume multiplication gates have exactly two input wires, which we call the left wire and right wire.
We don’t label the wires going from an addition to multiplication gate, nor the addition gate; we think of the inputs of the addition gate as going directly into the multiplication gate.
Considering this we should have only as many rows in each of the 3 R1CS matrix as there are number of gates.
Gabizon at the end of the Blog references Vitalik Buterin's post on the same - https://medium.com/@VitalikButerin/quadratic-arithmetic-programs-from-zero-to-hero-f6d558cea649
If you go to Vitalik's post, he creates a vector for each of the gates, both the addition gates & the multiplication gates. So each of his matrix ends up with 4 rows.
I assume there is some optimisation which Gabizon is doing by probably moving the addition gate data to the multiplication gate. However, his numerical example isn't as clear or detailed as Buterin's numerical example, so I am unable to figure out where it goes.
Also, by considering a different number of gates, their target polynomial should also be different - i.e. the gates being considered with each correspond to a root which goes into the target polynomial i.e. if there are 3 gates, the target polynomial $T(x) = (x-1)(x-2)(x-3)$. Whereas because of not considering the addition gate, you have only 2 gates, then your target polynomial will end up as $T(x) = (x-1)(x-2)$
Can someone who understands both examples explain how these 2 examples match up?