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have a project in which I have to implement an en/de-cryption structure using a standard AES block of 128-bits in VHDL and I think I'm a bit confused. So I'd like to ask some questions about AES and its modes of operation.

  1. When we say that we use a 128-bit key, does it mean that the data input's size is 128-bit or not? Generally can the block size be smaller than key?
  2. A block receives a plaintext. When the same block can receive a new plaintext?
  3. How can I perform each mode to make a system which encrypts information (parallel sequential)? I think that in NIST publication is clearly which modes can be performed pipelined or not. Although, I've been asked to find new ways of performance. What can I do? Please some help.
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  1. AES has a 128-bit block size, period. The valid key sizes are 128, 192, and 256-bits.

  2. I am not sure what you mean by that, a "block" is a 128-bit group of data, being the input and output to the cipher, it does not receive anything. Please revise that part of the question, and I will adjust my answer.

  3. CTR, OCB, and ECB are the only modes I know that can run encryption on blocks independent of eachother. CTR is the obvious choice for a fast secure implementation and turns the block cipher into a stream cipher. OCB is a more complex mode built on ECB, where both the input block and cipher output are modified using an incrementing counter generated from a nonce, and provides 1-pass authentication.

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  • $\begingroup$ So, for my first question, the data input's size depending on the key size? $\endgroup$ – George Karajohn Oct 8 '13 at 8:24
  • $\begingroup$ And for my second question, I mean "block cipher" $\endgroup$ – George Karajohn Oct 8 '13 at 8:25
  • $\begingroup$ The input of non key material into AES is always 128-bits, no exceptions. If the data needed to be input is not 128-bits, some kind of padding must be used to get it to 128-bits. A mode of operation is used to allow more than 128-bits of data to be encrypted, or to encrypt the block a different way $\endgroup$ – Richie Frame Oct 8 '13 at 8:32
  • $\begingroup$ With your clarification on item 2... it is still quite unclear. I would read that as "how does a block cipher encrypt more than 1 block", and the answer to that would be to use a mode of operation $\endgroup$ – Richie Frame Oct 8 '13 at 8:38
  • $\begingroup$ If I'm not wrong, every block cipher needs 10 cycle rounds to encrypt input's data. So, as i understand, that block cipher can't "receive" a new plaintext for 10 cycle rounds. And by cycle round i understand clock pulses. Am I wright? $\endgroup$ – George Karajohn Oct 8 '13 at 8:43
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  1. Input's size is only 128-bit for AES. When we use 192-bits or 256-bits key for AES the input's block size is 128-bit and not depend on the length of key.
  2. The real question is not clear. Refine.
  3. Go to the previous answers I want to add that there is CBC mode of AES. In CBC mode, each block of plaintext is XORed with the previous ciphertext block before being encrypted. This way, each ciphertext block depends on all plaintext blocks processed up to that point That is why we can't use parallel computing. To make each message unique, an initialization vector must be used in the first block.
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  • $\begingroup$ thank you for your answer. i tried to refine the 2 point of my question in a new question. I think i make a point of what i mean. $\endgroup$ – George Karajohn Oct 8 '13 at 9:41

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