# Verilog simulation & synthesis of Diffie-Hellman key exchange

Is there any freely available verilog implementaion of Diffie-Hellman key exchange?

I couldn't find anything using google. So, assuming its not there I started implementing on my own. The code is hosted at https://github.com/nulpoet/verilog_diffiehellman. Behavioral simulation in xilinx works. However it cannot synthesize the remainder(%) operator.

So, I does anybody know how to design a module for remainder operation in verilog that computes the remainder in a single clock cycle? Any links to literature discussing the algorithm would suffice.

Solution to any of the above two question would solve my problem.

• What bit lenth does your remainder operator work on? – Peter Green May 9 '16 at 3:46

Look on opencores within the vhdl section.

There are some older dos-era vhdl programs on simtel that have parsed-out statements so it might be more trouble than it is worth, but at least you could look under the hood of each function, grab what you need, run a lint checker etc, then perform verification.

• Just a friendly note - you don't need to use signatures in posts here - the signature in the bottom left gives you all the signature you need. This is to keep the page relatively clean. For more information have a look at this discussion. – user46 Apr 11 '12 at 7:27

So, I does anybody know how to design a module for remainder operation in >verilog that computes the remainder in a single clock cycle? Any links to >literature discussing the algorithm would suffice.

A nieve implementation would be something like.

parameter bitwidth;
input [bitwidth-1:0] a;
input [bitwidth-1:0] b;
output reg [bitwidth-1:0] result;
reg [(bitwidth*2)-2:0] bshifted;
reg [bitwidth-1:0] resulttmp;

reg [31:0] loopcounter

always @(posedge clk) begin
bshifted[(bitwidth*2)-2:bitwidth-1] = b;
bshifted[bitwidth-2:0] = 0;
resulttmp = a;
for (loopcounter = 0; loopcounter< bitwidth-1; loopcounter++) begin
if (bshifted < resulttmp) begin
resulttmp = resulttmp - bshifted;
end
bshifted[(bitwidth*2)-2] = 0;
bshifted[(bitwidth*2)-3:0] = bshifted[(bitwidth*2)-2:1];
end
result <= resulttmp;
end


The problem is that the ammount of logic this will generate is proportional to the bit width squared (that loop will be unrolled by the synthisis tool). At low bit widths this might actualy work but at high bit widths it's likely to end up producing a "can't fit design in device" or "timing requirements were not met" error.

I expect that for remainder operation on large numbers a single cycle implementation simply isn't practical.