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In article "A high performance ST-Box based unified AES encryption/decryption architecture on FPGA" (http://www.sciencedirect.com/science/article/pii/S0141933115001945) two 32Kb dual-port BRAMs are used. Each BRAM includes four coefficient groups: $T, T^{-1}, S, S^{-1}$ and each of this groups - according to article - needs 8Kb of memory.

AES Proposal (http://csrc.nist.gov/archive/aes/rijndael/Rijndael-ammended.pdf p.20) describes implementation of Look-Up Tables (T-Boxes) by generating four T-Boxes with different coefficients. Each T-Box uses 8Kb of memory ($256 \cdot 32 = 8192$), so for all four we need 32Kb.

As far as I know, each of dual-port BRAM's port uses same memory as the other, so one can obtain exactly the same value in each of two BRAM's ports using the same address.

  1. How is it possible, that four T-Boxes ($T_0, T_1, T_2, T_3$) of size 32Kb fitted in $\frac{1}{4}$ of 32Kb dual-port BRAM?

  2. How one can obtain correct coefficients for different elements knowing that 10bit address contains only 8bit value and 2 control bits (Encrypt/Decrypt and T-box/S-box select)? 8bit value is not conclusive when we are dealing with four types of T-Box.

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  • $\begingroup$ In the AES Proposal paper that you gave it says that "These are 4 tables with 256 4-byte word entries and make up for 4KByte of total space. ". So each table is 1 kb. Also, in the decryption you need 4 different tables too. So, at the end you have 8 tables which use 8 Kb memory in total. $\endgroup$ – Makif Apr 8 '16 at 11:58

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