I am faced with the task of generating a secure 256-bit IV for AES-CBC. I possess the following resources:
- A 32-bit microprocessor
- A 32-bit PRNG (can read/reseed)
- A 64-bit clock counter (can read)
The first one is unpredictable, but repeating. The second is non-repeating, but predictable. I am looking for a computationally lightweight way to combine them to achieve a high degree of unpredictable non-repeatability.
By "computationally lightweight" I mean that no cryptographic or other costly operations may occur. Only arithmetic operations on 32-bit registers, and not a lot of them for each IV.
Some working assumptions:
rate: $10^6$ IVs/second
rekeying: not faster than every few hours
UPDATE: The PRNG is an LSFR. Switching to CTR: I'll think about it. 256-bit IV: Yehuda is right, 128-bit it is.
I'm thinking of something along the lines of reseeding the PRNG with the 32MSB of the clock counter, reading a few values, then reseeding with the 32LSB and reading a few more.