# DES in hardware

Assuming that data is flowing in at a rate of n bits/sec and 1 iteration of DES can be performed in 1 clock cycle. Can we develop an expression for clock frequency, if DES were to be implemented using hardware?

Now we want to encrypt DES at a ratio of $n$ bits per second. If we divide $n$ by $64$ then we get the number of required cycles per second to permute $n$ bits, which is the frequency (as $n$ is already specified as bits per second).
So in the end you're just left with $$f = {n \over 64}$$