# DES in hardware

Assuming that data is flowing in at a rate of n bits/sec and 1 iteration of DES can be performed in 1 clock cycle. Can we develop an expression for clock frequency, if DES were to be implemented using hardware?

## 1 Answer

First about the required knowledge: obviously DES uses a 64 bit block. So a single DES operation permutes (encrypts or decrypts) 64 bits at a time. So this means DES is operating at 64 bits per cycle.

Now we want to encrypt DES at a ratio of $n$ bits per second. If we divide $n$ by $64$ then we get the number of required cycles per second to permute $n$ bits, which is the frequency (as $n$ is already specified as bits per second).

So in the end you're just left with $$f = {n \over 64}$$

• Just another doubt, if it take a single clock cycle for 1 iteration, then doesn't DES take 16 clock cycles (considering 1 clock cycle per iteration), then shouldn't the equation be f = n/4 – saahil24 Sep 12 '16 at 3:37
• You wrote "1 iteration of DES". DES internally uses 16 rounds. If they meant rounds, then they should have asked for "(a single iteration of) a round of DES". – Maarten Bodewes Sep 12 '16 at 8:27
• My bad, so if 1 round takes a single clock cycle, then does the equation n/4 hold true? – saahil24 Sep 12 '16 at 17:00
• @saahil24 Yep, that should be it. You'd need a 16 times higher frequency, so divide by something that is 16 times less. – Maarten Bodewes Sep 12 '16 at 17:21
• So, if 1 round takes a 1 clock cycle and some kind of hardware pipeline exists with 16 stages, the equation n / 64 is true. Whereas, if the 16 stages are executed sequentially, the equation is n/4. Is that logic correct? – saahil24 Sep 12 '16 at 17:31