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For a proof of work system a hash algorithm generates one pseudorandom index each round, in the same manner as RC4 and Spritz do. And it uses a bigger S-box, e.g. 2^20 numbers. The actual hash would be the first 32 output bytes of the stream cipher after dropping a certain number of rounds.

Would this be sufficient to get ASIC-resistance in a cryptocurrency?

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    $\begingroup$ Perhaps some more explanation would help. Yesteryear's ASIC is last year's FPGA which you can do today on a CPU /GPU. It's only incremental speed /footprint improvement. Wouldn't a simple larger s-box /memory be negated tomorrow by Moore's Law..? Do you know that there's a bitcoin.SE forum? They deal with alternative currencies as well. And they know ASIC manufacture /development. $\endgroup$ – Paul Uszak Jul 25 '17 at 1:31
  • $\begingroup$ Generally, people do not deal with the "exotic" ASICs, and this is where I do design. Basically, you are physically bound by a 2x2cm reticle. I can also get 4GiB on die via through vias so most things that are "memory hard" are not hard with custom hardware because all of my memory on-die. We were cranking things out on 14nm 5 years before it was a commodity process because we aren't selling widgets. For this reason, there's really not "ASIC" resistance in a general sense if you aren't in the constrained world. $\endgroup$ – b degnan Jul 25 '17 at 16:01
  • $\begingroup$ @bdegnan Sounds like a bit of an answer to me :-) $\endgroup$ – Paul Uszak Jul 25 '17 at 21:14
  • $\begingroup$ @PaulUszak well, I would need specifics of implementation for a proper hardware for an answer. Most people just think in the Intel/FPGA box. The real innovation is outside of that. Most everything that people consider to be "hard" I've seen an "easy" version of at the GOMAC conference. It's always just a matter of reference frame and available tools. $\endgroup$ – b degnan Jul 26 '17 at 11:48

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