There is generally a push to make algorithms and components constant time to be resistance to side channel attacks. For instance, AES-NI instructions take as many cycles as rounds; however, I can lower the CPU voltage and increase the clock speed until I see errors on the result. The circuits are only constant time if they satisfy the critical path propagation between latch boundaries.
When I read a paper that specifically says that it robust to side channel attacks because the algorithm is constant time, is the assumption that one does not have clock/voltage control?
To elaborate a bit on the boundaries that I mention, consider the following image that represents a pipeline of logic: In the image, there is a logic cloud that is operating on n-bits of information with a result. This is much like what a multiplicative inversion module looks like in hardware where you load the starting value and you then "latch" the result. The fundamental idea is that the clock line, CLK, is slow enough that you satisfy the worst-case propagation condition electrically. If I decrease the process voltage, and keep the clock the same speed, I can violate the path requirements. If I increase the clock speed for the same voltage, I also violate the requirements electrically.