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I am studying SHA3 in order to create a hardware implementation, preferably in verilog. I have downloaded VHDL reference implementation from https://keccak.team/hardware.html.

The code is great, and the reference document really detailed. However I cannot find any way to understand how the VHDL reference implementation receives the rate r and the capacity c parameters. I have understood the VHDL implementation is common for any Keccak-f[1600] transformation, but I do not understand how the code manages SHA3-256(M) or SHA3-512(M) executions.

In addition, is anyone aware of any additional complete Verilog or VHDL implementation?

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closed as off-topic by e-sushi Apr 3 '18 at 20:07

This question appears to be off-topic. The users who voted to close gave this specific reason:

  • "Programming questions are off-topic even if you are writing or debugging cryptographic code. Unless your question is specifically about how the cryptographic algorithm, protocol or side-channel (mitigation) works, you should look into asking on Stack Overflow instead." – e-sushi
If this question can be reworded to fit the rules in the help center, please edit the question.

  • $\begingroup$ Maybe rate and capacity got hardwired into the implementation of each SHA-3 instance. And this may be a programming / hardware design question suitable for another site. $\endgroup$ – DannyNiu Apr 3 '18 at 3:52