I am studying SHA3 in order to create a hardware implementation, preferably in verilog. I have downloaded VHDL reference implementation from https://keccak.team/hardware.html.
The code is great, and the reference document really detailed. However I cannot find any way to understand how the VHDL reference implementation receives the rate r and the capacity c parameters. I have understood the VHDL implementation is common for any Keccak-f transformation, but I do not understand how the code manages SHA3-256(M) or SHA3-512(M) executions.
In addition, is anyone aware of any additional complete Verilog or VHDL implementation?