I implemented DES Coder in VHDL using ISE IDE by Xilinx in sequential architecture which was pretty easy and straightforward. Now my task is to do the same using pipelined architecture so that the whole thing will work with maximum possible clock frequency. I read numerous papers from IEEE site concerning pipelined DES but still I couldn't fully get my head around the topic. What is different? So far I understood that I have to make it so:
There are no complex instructions in the code of every module. For example if I had instruction "x <= a * b * c" I'd have to break it down to two instructions in for loop and when iterator is equal to 0 do "temp <= a * b" and when iterator is equal 1 do "x <= temp * c". Just an example but shows the way of thinking - instead of one complex instructions - many simple ones (using loops or for generate).
Once input A gets to Feistel Round 2 then input B (for example next 64-bit plaintext word) gets loaded immediately to Feistel Round 1 and so on allowing us to process 16 words "quasi simultaneously". That would require us to have a synchronizing register before and after every Feistel Function module. Also I read something about modules for "pipeline" and "control module" although none of the articles mentioned how they worked. To be honest I have zero ideas about how to implement this part.
Are my presumptions wrong at any of the 2 points? Could anyone please explain to me in detail how to bite into this problem? Does anyone have an example of working pipelined DES Coder/Decoder on FPGA? I will be thankful for every bit of help.