# What does “Clocked” mean in alternating step generators

In the wiki article, it says "An ASG comprises three linear-feedback shift registers, which we will call LFSR0, LFSR1, and LFSR2 for convenience. The output of one of the registers decides which of the other two is to be used; for instance, if LFSR2 outputs a 0, LFSR0 is clocked, and if it outputs a 1, LFSR1 is clocked instead."

I would appreciate it if someone could explain how an ASG works and what it means for the LFSR to be clocked or left alone and if possible, a small example to show this.

Clocked is an electronics term and here it applies to the LFSR's implementations;

Assume that the LFSRs are implemented with D-FLip-Flop that can store values in bits. At each clock, the waiting input (D) passes the output (Q) and in LFSRs that go to the next cell. This is the shift operation.

The clock of the system simultaneously acts on D-fLip-flops if not controlled by some other logic. If one controls the clock with an additional logic/value as in ASG then according to the logic, D-fLip-flop may not be clocked that result in keeping the same values. The LFSR still outputs the same value as the previous clock.

In software you can consider this like;

Have an LFSR class that hast two functions apart from the constructor, destructor, and some other utilities like the current step value;

• advance() -> that shifts the LSFR and feedback the new value according to the feedback polynomial
• getOutput()

According to control value, one call advance() then getOutput() or just getOutput(). The latter is keeping the previous values.

• Thank you very much for the explanation, this helps a lot. I have one more question though if that's okay. When clocked, how is the output from the LFSR calculated? I know LFSR have output sequences. So if the input going into LFSR R2 is a 0 and the sequence for the LFSR is a 1 what would the output be? Is some time of logic gate used? Thank you :) – ZazzyCola Mar 25 at 22:45