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I was reading the abstract of "Non-deterministic Processors" paper by "David MayHenk L. MullerNigel P. Smart", in the abstract, they have mentioned the Kocher paper about "Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems"

What is the application of Non-deterministic Processors on a side-channel attack?

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    $\begingroup$ link.springer.com/chapter/10.1007/3-540-47719-5_11 $\endgroup$ – kelalaka May 26 '20 at 22:38
  • $\begingroup$ @kelalaka I did read the abstract but not the entire book. $\endgroup$ – R1w May 26 '20 at 22:41
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    $\begingroup$ so, read some more of the book before asking people based on just the abstract. maybe then you can ask a more sensible and considered question. $\endgroup$ – kodlu May 26 '20 at 23:29
  • $\begingroup$ @kodlu Actually I was going to read the paper but I had to pay 30 dollars for the pdf file, then I thought, how about asking experts? how about you help me more? $\endgroup$ – R1w May 26 '20 at 23:45
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    $\begingroup$ @R1w have you ever head the barrier remover scihub? $\endgroup$ – kelalaka May 27 '20 at 6:28
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Non-deterministic processors are generally sold as a method to vary processor timing and power. To my knowledge they are theoretical as synchronous systems, as I have never seen any literature where one has actually been constructed. The premise is that if you have varying instruction order, and completion time, you then have some level of robustness to side-channel attacks. It is important to note that these are still synchronous systems. The closest work that I know to this where hardware exists was body of probabilistic computing work by Palem, George and Marr.

You could easily make a non-deterministic system with asynchronous logic. When I make asynchronous systems, creating noise is trivial because of the completion trees, and I do add random noise to the completion logic to slow it down as a verification of robustness against EMI. This method would make the circuits robust to a side-channel attack due to random completion times for all logic. Having said that, the dual-rail encoding of asynchronous circuits means that you cannot have a power attack, but only a timing attack. You could size the completion trees so that they always required the same time; however, that would eliminate the speed gains of the asynchronous circuits.

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    $\begingroup$ While the processing time is huge. like RSA and ECC without the M. ladder, this is not going to solve the side channel issue. The noise should be so big that the noise should be the actual process and the actual process should be the noise. $\endgroup$ – kelalaka May 27 '20 at 6:26
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    $\begingroup$ @kelalaka which part? I do not believe you can solve the side channel issue with probabilistic pipelines. The asynchronous logic is robust to power attacks, and you cannot see the pipelines without wire access, so it pretty much solves side-channel everything but no one uses it as it's a HUGE hassle to implement. $\endgroup$ – b degnan May 27 '20 at 11:59
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    $\begingroup$ It was not really great idea. Consider that most of the time the CPU is doing noise processes. Then computes seldomly as noise:) $\endgroup$ – kelalaka May 28 '20 at 9:01
  • $\begingroup$ @kelalaka gotcha. right on $\endgroup$ – b degnan May 28 '20 at 10:27

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