While reading specsheets for NXP processors (example mention in this PDF) the other day I saw the mention of the Indexed Code Book mode (ICB) for their AES acceleration hardware - the only mode they claim side-channel resistance for.

However, my search attempts have failed me and I could not identify a definition of this mode.

So, how is Indexed Code Book Mode defined?

I also found a related (?) LRICB mode if that helps in this PDF.

  • 1
    $\begingroup$ So far I have found this which is clear about the aim, if not the how: "ICB is a form of CTR cipher mode, but its purpose is to be Side Channel Analysis resistant. It uses a method which is a counter-measure to various Side Channel attacks such as SPA/DPA/DPX (power analysis) and emanation analysis. ICB is slower than normal AES ECB and CTR mode, as a consequence of being SCA resistant. This mode can be used for extra-secure on-chip storage for sensitive information." $\endgroup$
    – fgrieu
    Feb 22, 2021 at 11:12
  • $\begingroup$ Addition: your guess is as good as mine about if ICB is LRICB as described in the later reference, or that with some step taken out or simplified. $\endgroup$
    – fgrieu
    Feb 22, 2021 at 15:26


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