A fan-in $2$ and fan-out $1$ Boolean circuit is a circuit consisting of $\operatorname{AND}$, $\operatorname{OR}$ and $\operatorname{NOT}$ gates where number of inputs to $\operatorname{AND}$ and $\operatorname{NOT}$ are constrained to be $2$ and number of output gates any of the gates can be connected to is $1$.
I am wondering if $\operatorname{SHA-256}$ is implemented as a multi-output (all hash bits computed by one circuit) fan-in $2$ Boolean circuit what would its depth be?
Can its depth be in the low $10$s while the number of gates could be in say range $10^6$ to $10^9$?
Direct sequential implementation of rounds would warrant a depth of at least $64$ since $\operatorname{SHA-256}$ employs $64$ rounds.
It has to be a clever optimized design.