I have been looking into error-correcting codes in lattice, I am specifically hoping to find some information on hardware implementations for the NIST PQ PKE/KEM finalists (Saber, CRYSTALS-Kyber, NTRU).
I was reading this article on Timing Attacks on Error Correcting Codes in Post-Quantum Schemes and it mentions:
Kyber  and Saber  choose their parameters so that their failure probability is small enough without need for ECC. NTRU  and NTRU prime  even eliminate all decryption failures without using any ECC. These schemes are therefore not vulnerable to side-channel analysis on ECC and do not need the extra protection against these types of attacks.
I also understand the Lattice codes are also referred to as "Sphere packing". Something I have read about conceptually, although I am not sure how it works practically.
However, I have also seen a few articles (such a this) that have been published recently about RLWE (Ring-Learning with Error) that tackle error correction and fault detection in that space, however none of the finalists use RLWE (as far as I can tell?)
My question is somewhat broad: I want to investigate ECC/fault detection in hardware (or more accurately their lattice counterparts), specifically with one of the NIST finalists. Does anyone have any insights into this sector of Lattice Cryptography? I am very new to this field (I'm a student, looking to define a thesis topic) but any insights would be appreciated.