I'm trying to understand a verilog AES implementation. I know the order of the AES encryption steps to be as shown:
However the code I see doesn't do this.
They do the following flow graph: at the beginning of the encryption state
is loaded with newstate
or the plaintext. The round
is set to max
and is decremented each round.
They then do the following set of operations for each round until round
reaches 0. The internal variables are inside brackets and the operations are without.
(state) -> (sbbi) -> sbox -> (sbbo) -> shift -> (shro) -> mix -> (mxco)
They select the output of each round based on the round variable, this is used to set the newstate
which sets the new input state:
if round == 0:
(state)
if round == max:
(shro)
else
(mxco)
The problem I'm having is I'm expecting to see the operations Sub
, Shift
, Keyadd
for the last round (0 in this code). But that is not what it does and even taking the output of round 1 and seeing that as the 'last round' is wrong as that does a double key add.
round
is getting decreased? maybe this is from the decryption setting? you also probably missed the add-key somewhere (hardcoded bitflips perhaps?). Otherwise looks legit $\endgroup$KEYSCHED
state and not in theDECRYPT
state (which I had interpreted as dual purpose with a terrible label). Thus the counter is indeed incrementing and thus the code is working as expected $\endgroup$