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Nov 26, 2017 at 23:11 vote accept b degnan
Nov 26, 2017 at 11:31 answer added dusk timeline score: 3
Nov 26, 2017 at 1:44 history tweeted twitter.com/StackCrypto/status/934598799896571904
Nov 25, 2017 at 23:06 comment added SEJPM @back_seat_driver normally with flip-flops, data is stored on a clock edge, ie on a low-to-high voltage change of the clock input. Shortly after this point in time the output of the flip-flop has the stored value at which point the subsequent combinatorial logic gates (AND, OR, NOT, ...) start propagating the result of the new signal(s). Then at the next low-to-high clock edge, the current data at the latch's input is "written". If this happens before the data could propagate through the logic your overall expected clock count for the computation will be off.
Nov 25, 2017 at 22:53 comment added Q-Club @SEJPM So the data can be read faster than it can be written?
Nov 25, 2017 at 19:59 comment added SEJPM @back_seat_driver In hardware design you have latches which are the default storage over multiple clock cycles. A critical path in a combinatorial circuit is the path through the gates with the longes delay. Thus if your propagation delay on your critical path is longer than a cycle, the value may not arrive during the current cycle at the storage.
Nov 25, 2017 at 19:03 comment added b degnan @CodesInChaos I guess that must be true, but it also means that the general claims are poor as they aren't well defined. Authors seem to be terrible at mention this specific assumption.
Nov 25, 2017 at 18:57 comment added b degnan @back_seat_driver I put in an image.
Nov 25, 2017 at 18:57 history edited b degnan CC BY-SA 3.0
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Nov 25, 2017 at 18:32 comment added Q-Club Can you elaborate a little on "critical path propagation between latch boundaries"
Nov 25, 2017 at 17:28 comment added CodesInChaos It's only about software side channels, not hardware side channels
Nov 25, 2017 at 16:43 history asked b degnan CC BY-SA 3.0