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Which techniques could be applied to AES to prevent these kind of attacks?

I can just think of creating noise with a parallel process for random computation, so the signals have the combination of that process and the crypto process.

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    $\begingroup$ Depends on hardware at hand, which is not described. $\endgroup$ – fgrieu Oct 20 '18 at 20:01
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    $\begingroup$ Why does it depend on hardware? Sorry Im just learning about this topic. $\endgroup$ – Mr. Goferito Oct 20 '18 at 20:18
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    $\begingroup$ @Mr.Goferito This is a very open question. The answer is different depending on if you running on a CPU, FPGA, etc. As an example, my async ICs do not suffer from power attacks, so you cannot even cause this attack. $\endgroup$ – b degnan Oct 22 '18 at 12:52
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  • DPA-resistant cores

  • Masking (attempt to conceal the intermediate date processed by modifying the data such that the complete secret is never processed simultaneously)

For example you can introduce s-box shuffling in AES as a software solution to decrease the likelihood that the attack succeeds.


Pseudo Code s-box shuffling from Figure 2 of www.indjst.org/index.php/indjst/article/download/61626/48132:

Begin
// The assignment of Round Key
Byte RK[11][16]
// The generation of Random Value
shuffle = rand()%8
// The execution of Key Expansion
KeyExpansion(Byte Masterkey[16], Byte Roundkey[11][16])
// The assignment of the execution of eight-shuffling AES
(*ptr_shuffle[8])(Byte PT[16], Byte RK[11][16], Byte CT[16])
ptr_shuffle[0] = &AES_Original1
ptr_shuffle[1] = &AES_Original1_Macro
ptr_shuffle[2] = &AES_Original2
ptr_shuffle[3] = &AES_Original2_Macro
ptr_shuffle[4] = &AES_Bertoni
ptr_shuffle[5] = &AES_Bertoni_Macro
ptr_shuffle[6] = &AES_T-Table
ptr_shuffle[7] = &AES_T-Table_Macro
// The execution of eight-shuffling AES
ptr_shuffle[shuffle](PT, RK, CT))
End 
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